OS Exam Prep
Random notes from my exam prep I’m saving for the future.
- page fault page replacement
- deadlock
- logical addressing vs. physical addressing
- external memory fragmentation
CPU can only read directly from RAM.
To read from disk, disk must be read into RAM first.
Virtual memory solves three problems:
- Not enough memory (cant access addr beyond max addr)
- Memory fragmentation (hard to write programs that split memory)
- Security (programs could corrupt each others state)
Virtual memory creates individual (logical) address space for each program. Virtual address space is mapped to physical address space (with translation lookaside buffers). Virtual memory can map data across multiple devices (like disk if mem space exceeded)
- Swap memory = memory on disk
- Page = uniformly sized portions of memory
- Page fault = we need to load page from swap
Page Faults
A frame (in main memory) can hold one page.
If mem exceeded, then load from swap. Before loading from swap, eject a page from memory (which depends on the replacement algorithm) Write this page to disk if dirty (having been written to after loading from disk) Then load desired page from disk and continue execution. When a page is ejected, it is set to invalid in the page table.
- External fragmentation happens when there are holes of unallocated memory.
- Internal fragmentation happens when you allocate too much memory.
Over-allocation is more or less a page fault, which produces page replacement
In context of page replacement, the following algoithms mean the following:
- FIFO = the first (still present) frame that entered main memory is replaced
- LRU = the first (still present) frame that was requested is replaced
- OPTIMAL = the page (in main memory) that not will be used for the longest time is replaced
That means FIFO and LRU looks backwards, while OPTIMAL looks forwards. LRU and OPTIMAL both share that they are based on the reference string. FIFO is based on keeping a queue. If no pages currently in memory are requested in the future, OPTIMAL can fallback to FIFO. OPTIMAL is however theoretical (CPU’s can’t predict the future).
- Number of page faults = number of page replacements
- Hit ratio = number of hits divided by number of page faults
Why CPU Scheduling?
- CPU Scheduling is necessary for running more than one program concurrently.
- To do many things at once, the CPU must constantly switch tasks with minimally wasted time.
- Scheduling algorithms are important for doing this as efficiently as possible.
Definitions
Waiting time is the sum of all time processes spend not being processed. Turnaround time is the time it takes to complete a process. Throughput is the amount of processes a CPU can complete in a given time. Throughput time is the time it took to complete a number of processes.
Deadlock refers to the following:
- Mutual Exclusion (processes competing over resource only one can use at a time)
- Hold and Wait (processes holding resources can request other resources and wait until its available)
- No Preemption (a process must release its resources voluntarily)
- Circular Wait (process A holds resource A waiting for resource B held by process B waiting for resource A to become available)
Stack is not shared between threads in a multithreaded process.
Stats for Pre-emptive priority scheduling example:
PID | Arrival | Burst | Priority |
---|---|---|---|
P1 | 0ms | 11ms | 2 |
P2 | 5ms | 28ms | 0 |
P3 | 12ms | 2ms | 3 |
P4 | 2ms | 10ms | 1 |
P5 | 9ms | 16ms | 4 |
How I think it would evaluate:
- P1 for 2ms (9 left)
- P4 for 3ms (7 left)
- P2 for 28ms (done)
- P4 for 7ms (done)
- P1 for 9ms (done)
- P3 for 2ms (done)
- P5 for 16ms (done)
Turnarund Time = Completion time - Arrival time Waiting Time = Turnaround Time - Burst Time
Completion Time
- P1 CT = (2 + 3 + 28 + 7 + 9) = 49
- P2 CT = (2 + 3 + 28) = 33
- P3 CT = (2 + 2 + 28 + 7 + 9 + 2) = 51
- P4 CT = (2 + 2 + 28 + 7) = 40
- P5 CT = (2 + 2 + 28 + 7 + 9 + 2 + 16) = 67
- AVG CT = (49 + 33 + 51 + 40 + 67) / 5 = 48
Turn-around Time
- P1 TT = 49 - 0 = 49
- P2 TT = 33 - 5 = 28
- P3 TT = 51 - 12 = 39
- P4 TT = 40 - 2 = 38
- P5 TT = 67 - 9 = 58
- AVG TT = (49 + 28 + 39 + 38 + 58) / 5 = 42.4
Waiting Time
- P1 WT = 49 - 11 = 38
- P2 WT = 28 - 28 = 0
- P3 WT = 39 - 2 = 37
- P4 WT = 38 - 10 = 28
- P5 WT = 58 - 16 = 42
- AVG WT = (38 + 0 + 37 + 28 + 42) / 5 = 29
Deadlock prevention Banker’s
Available = Amount of resource instances - Allocated Amount of resource instances = 5
PID | Allocation | Request | System | Available | A - R |
---|---|---|---|---|---|
A B C | A B C | A B C | A B C | A B C | |
P0 | 1 2 1 | 1 0 3 | 5 5 5 | 0 1 2 | X |
P1 | 2 0 1 | 0 1 2 | 2 1 3 | 0 0 2 (P1 first) | |
P2 | 2 2 1 | 1 2 0 | 3 3 4 | 1 1 0 (P0 second) | |
5 5 5 | 2 1 4 (P2 third) |
P1 -> P0 -> P2 (no deadlock)